摘要
采用动态双轨逻辑实现安全芯片中密码运算模块可以有效抗功耗攻击,但也存在面积、功耗以及运算性能等方面的弱点.本文采用动态双轨与静态单轨逻辑混合设计以实现密码运算模块,并且采用了非对称时钟,这样可达到较好的性能折衷.本文给出了混合设计所遵循的设计约束和时序约束,设计实现了一个动态双轨标准单元库,并给出了一个抗功耗攻击的安全芯片半定制设计流程.根据这个设计流程,本文设计实现了一个3DES协处理器,其中8个S盒全部采用动态逻辑实现,其余部分采用静态逻辑实现;实验结果表明本文给出的混合设计方法和对应的设计流程是完全可行的.
Dynamic dual-rail logic （DDRL） consumes nearly constant energy, so it is able to resist power analysis. Because of the nature of DDRL, dynamic dual-rail circuit causes extra cost of area, power and performance in contrast with static eircuit. In order to achieve optimized performance and security, hybrid design based on DDRL and static logic is employed. Besides, asymmetric clock is used to drive both DDRL and static registers. Design rule and timing constraints of this kind of hybrid design are presented. Based on a DDRL standard cell library, a semi design flow is presented. According to this design flow, this paper implements a Tri-Des coprocessor. The 8 S-boxes of this coprocessor are dynamic circuits, while the rest is static. The simulations show that hybrid design and the presented design flow are applicable and effective.
出处
《小型微型计算机系统》
CSCD
北大核心
2007年第5期935-939,共5页
Journal of Chinese Computer Systems
关键词
功耗攻击
防护技术
动态双轨逻辑
混合设计
半定制设计流程
power analysis
protected implementation
dynamic dual-rail logic
hybrid design
semi-custom design flow
