摘要
本文针对在语音、视频等信号处理中出现的变速率信号处理,提出了一种新型的高速高效可重构流水线乘法器电路,并在0.25μm工艺条件下对电路进行了仿真。该电路通过控制流水级数处理变速信号,可有效地节约电路资源约34%,同时可保证频率达1.8GHz的高运算速度。
This paper brings forward a new high speed and efficiency re-configurable pipeline multiplier, on the alterable velocity signal process of sound and video. The circuit is simulated under 0.25μm CMOS process. The circuit avoids the resource waste of 34 percent for the alterable velocity signal process and remains the high speed of 1.8GHz by controling the pipeline number.
出处
《电路与系统学报》
CSCD
北大核心
2007年第3期33-36,共4页
Journal of Circuits and Systems
关键词
可重构
高速
乘法器
流水线
re-configurable
high speed
multiplier
pipeline
