摘要
利用DVI接口的同步控制信号生成内存写入地址,帧频触发信号控制内存读取地址的设计思想,在FPGA中实现了从任意帧频的数字视频源转换到50Hz或60Hz帧频.给出了帧频转换器的基本硬件结构,和实用的设计方法,并讨论了数据缓冲区设置深度与内存操作带宽的关系.
The main goal of this paper is to introduce a method on how to realize the digital video asynchronous frame rate converter in a FPGA chip. The DVI port of PC is one common way to get the digital video signal. The DVI scan synchronous signal such as Vsync, DE and Pixel clock are used to generate the write addresses of its Pixel data, and the frame rate synchronous pulse is generated to synchronize the video Synthesizer, cache management units, memory controller and all other logic modules in the FPGA chip. Not only the 50 Hz or 60 Hz frame rate can be realize, through this simple but useful method, any frame rate can be converted which are limited by the memory data bandwidth. A dual channel with spread word length memory architecture and the cache depth setting skills are also introduced in this paper.
出处
《电子器件》
CAS
2007年第3期1064-1067,共4页
Chinese Journal of Electron Devices
