摘要
提出了一种基于Costas环(科思塔斯环)载波同步的改进环路,它具有可变环路增益和可变环路带宽。与传统的Costas环相比,改进环路增加了频差估计、增益控制和环路锁定检测三个辅助电路。该方法能较好地处理环路带宽、稳态相位误差与环路增益之间的关系,在FPGA上已成功实现。
In this paper, a new carrier synchronizer loop with variable loop gain and loop bandwidth has been discussed. Compared with the traditional loop, three accessional circuits are employed： frequency offset estimate circuit, gain control circuit and loop status detector circuit. The relationship amongloop bandwidth, steady -state jitter and loop gain can be well -handed. The new loop has been implementedon FPGA.
出处
《微处理机》
2007年第3期108-110,113,共4页
Microprocessors
