摘要
提出了一种适用于JPEG2000标准中并行通道编码的Embedded Block Coding with Optimized Truncation (EBCOT)高速MQ编码器的硬件架构。首先对JPEG2000标准流程的标码流程选择和字节输出等流程进行改进,使之更适应于硬件实现,并提出一种区间重整时对前导零位数的更简洁的判断方法和电路实现,充分利用硬件并行性,提高了编码速度。进而提出了四级流水的MQ编码器硬件架构,有效提高了MQ编码速率,充分满足并行通道编码的要求。
This paper presents a high - speed hardware architecture of a MQ coder for parallel pass coding EBCOT unit of JPEG2000 encoder. Firstly the coding flow is optimized to adapt to the conditions of hardware implementation and make full use of the parallel feature of the hardware. A new method to count the leading zero in renormalization flow is proposed, which is simpler and faster. Then a hardware architecture based on four-level pipeline is presented. The speed of the hardware engine reaches 225MHz, which improves the efficiency of MQ coder and meet the demands of parallel pass coding EBCOT.
出处
《信息技术》
2007年第5期51-53,57,共4页
Information Technology
