摘要
介绍一种采用FPGA设计实现的ADPLL的结构及特点,并用该锁相环产生SDH设备的外同步时钟。由于该锁相环的负反馈时钟采用了初始受控分频设计、并采用了合理的环路滤波算法,该ADPLL同传统的数字锁相环(DPLL)一样,在参考源切换过程中输出时钟平滑稳定;同时也和传统的模拟锁相环(APLL)一样,在锁定状态下有稳态相差。对输出时钟的测试表明,该ADPLL产生的SDH外同步输出时钟满足系统的应用要求。
The structure and characteristics of an All-digital Phase Locked Loop（ADPLL） designed with FPGA are presented, and we get the exterior synchronization clock of SDH Device with the ADPLL. The ADPLL has steady output clock as traditional Digital PLL （DPLL） when source changed; at the same time, it has steady-state error as traditional Analog PLL（APLL） when locked; because we adopted a means of Control Divider initially to design feedback clock of Phase Locked Loops, and a close filter arithmetic was used. Test results of output clock show that the exterior synchronization clock of SDH Device with the ADPLL design is fit for SDH device system.
出处
《微计算机信息》
北大核心
2007年第05Z期181-183,共3页
Control & Automation
