摘要
目前,多数基于混沌加密的实现方案局限于软件领域(该领域下数据是串行处理的),然而当吞吐量和安全性成为主要问题的时候,硬件实现更优越。根据目前的混沌伪随机位序列发生器的并行加密算法,本文介绍该算法的FPGA设计方案。
Currently, most achieving projects based on chaotic encryption limited to software area. However, when throughput and security become the major problems, the hardware is more superb. Bases on the current parallel encryption algorithm of chaotic pseu- do-random sequence generator, in this paper, we will introduce the FPGA design of the algorithm.
出处
《微计算机信息》
北大核心
2007年第29期179-181,共3页
Control & Automation
基金
校青年科学研究基金资助(06A15)
