摘要
基于标准n阱0.6μm CMOS工艺条件,设计了一种用于高阶∑ΔADC的基准源结构。该电路在传统带隙基准电路的基础上,采用三个纵向晶体管串联的形式减小运放输入失调电压对基准电压的影响同时采用高增益运放来降低基准电流的失配。另外设计了启动电路以确保基准电路能正常工作。仿真结果表明此电路电源抑制比为73 dB,温度系数为9.6×10-6/℃。经过对系统的分析与验证,该电路完全满足高阶∑ΔADC对其性能的要求。
A bandgap voltage reference used in high-order ∑Δ ADC based on standard n-well 0.6 μm CMOS process was given.The influence of the offset voltage of op-amp on the reference voltage was decreased using 3 vertical BJT in series and the current mismatch was reduced by high-gain op-amp.The start-up circuit was design for the bandgap voltage reference circuit working normally.Results from simulation show that the circuit has a PSRR of 73 dB and accuracy of 9.6×10^-6/℃.According to the analyses and simulation of system,the circuit completely meets the requests of high-order ∑Δ ADC.
出处
《半导体技术》
CAS
CSCD
北大核心
2007年第10期882-885,共4页
Semiconductor Technology
