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低相位噪声压控振荡器设计 被引量:1

Design of a Low-Phase-Noise VCO
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摘要 分析了LC压控振荡器(VCO)相位噪声,通过改进电路结构,采用PMOS和NMOS管做负阻管,在尾电流源处加入电感电容滤波,优化电感设计,设计了一种高性能压控振荡器。采用TSMC 0.18μm IP6M CMOS RF工艺,利用Cadence中的Spectre RF工具对电路进行仿真。在电路的偏置电流为6 mA、电源电压VDD=1.8 V时,输入控制电压为0.8-1.8 V,输出频率变化为1.29-1.51 GHz,调谐范围为12.9%,相位噪声为-134.4 dBc/Hz@1MHz,功耗仅为10.8 mW。 According to the analysis of the phase noise of LC VCO, a kind of high performance VCO was designed through reforming the structure of the circuit. PMOS and NMOS were used as negative resistances together in this circuit. LC was used for noise filtering in the tail current source. Inductance was optimized. The circuit was designed in TSMC 0.18 μm IP6M CMOS RF process, and simulated by the spectre RF in Cadence at supply voltage of 1.8 V. The current source is 6 mA, and the range of control voltage is 0.8-1.8 V. The output frequency is 1.29-1.51 GHz, and ttming range is up to 12.9%. Phase noise is - 134.4 dBc/Hz at an offset of 1MHz. The static power of the circuit is only 10.8 mW.
出处 《半导体技术》 CAS CSCD 北大核心 2007年第11期992-994,共3页 Semiconductor Technology
基金 湖南省自然科学基金资助项目(05JJ30115)
关键词 压控振荡器 相位噪声 电感电容滤波 互补MOS VCO phase noise LC filter CMOS
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参考文献6

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