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一种基于高频时钟产生电路的DLL的研究 被引量:2

Research of DLL Based High Frequency Clock Generator
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摘要 本文给出了一种采用自偏置技术的低抖动延迟锁相环,可应用于高频时钟产生电路。分析了环路带宽和工作频率的关系,并给出了各模块具体的电路设计。在0.35μm标准CMOS工艺、3.3V工作电压下进行了模拟仿真,在100MHz的参考输入频率下,DLL锁定时间为1μs,VCDL输出的相位抖动为17μs,倍频器输出的相位抖动为90μs。 In this paper, a low-jitter process-independent DLL(delay locked loop) based on self-biased techniques is presented. It can be applied in high frequency clock generator. An analysis on the relationship between the loop bandwidth and the operation frequency and the circuit design of DLL is described. Since the 0.35um CMOS technology and 3.3V voltage supply, the locking time is approximately 1μs, the peak-to-peak jitter of the VCDL output and FM output are ps and ps with 100 MHz input.
出处 《微计算机信息》 北大核心 2007年第35期270-272,共3页 Control & Automation
基金 上海市科委国际合作发展基金资助(055207041)
关键词 锁相环 延迟锁相环 压控延迟线 鉴相器 电荷泵 倍频器 PILL, DLL, VCDL, PFD, Charge Pump, Frequency Multiplier
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参考文献6

  • 1David W. Boerstler, A Low-Jitter PLL Clock Generator for Microprocessors with Lock Range of 340-612 MHz, J. Solid State Circuits, vol.34, no.4, April 1999
  • 2李肃刚,杨志家.一种改进的全数字锁相环设计[J].微计算机信息,2005,21(09S):42-43. 被引量:20
  • 3John G. Maneatis, Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL, IEEE J. Solid State Circuits, vol.38, no.11, November, 2003
  • 4David J. Foley, CMOS DLL Based 2V, 3.2ps Jitter, 1 GHz Clock Synthesizer and Temperature Compensated Tunable Oscillator, IEEE J. Solid State Circuits, vol.36, No.3, MARCH 2001
  • 5Chulwoo Kim, A Low-Power Small-Area 7.28-ps-Jitter 1-GHz DLL-Based Clock Generator, IEEE J. Solid State Circuits, vol.37, No. 11, November 2002
  • 6John G. Maneatis, Low-jitter Process-independent DLL and PLL based on self-biased techniques, IEEE J. Solid State Circuits, vol.31, no.11, November 1996

二级参考文献2

  • 1RolandE.Best Phase-Locked Loops design, simulation, and applications’[M].北京:清华大学出版社,2003年12第一版..
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共引文献19

同被引文献31

  • 1张沛超,高翔.数字化变电站系统结构[J].电网技术,2006,30(24):73-77. 被引量:206
  • 2王文俭,赵征.辐射骚扰场强测试方法简述[J].中国无线电,2007(1):48-50. 被引量:2
  • 3普鑫.利用扩频技术抑制开关电源电磁骚扰[J].安全与电磁兼容,2006(6):71-72. 被引量:3
  • 4李九虎,郑玉平,古世东,须雷.电子式互感器在数字化变电站的应用[J].电力系统自动化,2007,31(7):94-98. 被引量:188
  • 5Chien G, Gray P t A 900--MHz local oscillator u- sing a DLL-based frequency multiplier technique for PCS applications [J]. IEEE Journal of Solid-State Cir- cuits, 2000(35) : 1996-1999.
  • 6Kim C, Hwang I C, Kang S IVL A low-power smallar- ea_7. 28ps jitter 1 GHz DLL-based clock generator [J]. IEEE J Solid-State Circuits, 2002,37 (11) : 1414- 1420.
  • 7Farjad-Rad R, Dally W, Ng H T. A low-power multi- plier DLL for low-jitter multigigahertz clock generation in highly integrated digital chips [J]. IEEE J Solid- State Circuits, 2002,37(12) : 1804-1812.
  • 8Tai-Cheng Lee, Keng-Jan Hsiao. The design and anal- ysis of a DLL-based frequency synthesizer for UWB application[-J. IEEE J Solid-State Circuits, 2006,41 (6) : 1245-1252.
  • 9Kyunghoon Chung, Jabeom Koo, Soo-Won Kim, et al. An anti-harmonic, programmable DLL-based frequency multiplier for dynamic frequency sealing [J]. IEEE A- sian Solid-State Circuits Conference, 2007 : 276-279.
  • 10Jin-Han Kim, Young-Ho Kwak, Seok-Ryung Yoon, et al. A CMOS DLL-based 120MHz to 1.8GHz clock generator for dynamic frequency sealing [J]. IEEE J. Solid-State Circuits, 2006,41 (9) : 516-614.

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