摘要
实现了一种应用于UART中的自适应波特率发生器的设计。设计通过使用计数器和边沿检测器对串行线路上的一个低电平周期进行精确计数,然后经过一系列比较迭代,最终得出串行线路数据波特率。利用Quartus软件工具完成电路物理设计、仿真及综合,结果表明电路能正确地探测出串行数据波特率。最后将电路实现于CycloneII系列FPGA上。运用该电路可以简化UART接收器部分设计。
A novel design of auto-tuning baud rate generator for UART （universal asynchronous receiver/ transmitter） was realized. A counter and a edge detector were used for counting the numbers on a low level period of serial line, repeating this process some times, then the boud rate would be gotten. The Quantus solf ware was used to complete the circuit design, simulation and synthesis. The result indicates that the circuit can detect the serial data baud rate exactly. This circuit was implemented on the CycloneII series FPGA. This circuit can simplity the part of UART receiver design.
出处
《半导体技术》
CAS
CSCD
北大核心
2007年第12期1052-1055,共4页
Semiconductor Technology
基金
国防科技重点实验室基金支持项目(51433020105DZ6801)
