摘要
A high-accuracy,low-dropout （LDO） voltage regulator is presented. Using the slow-rolloff frequency compensation scheme, the LDO effectively overcomes the stability problem, facilitates the use of a ceramic capacitor, and improves the output voltage accuracy, which is critical for powering high-performance analog circuitry. The slow-rolloff compensation scheme is realized by introducing three pole-zero pairs, including the proposed polezero pair and sense zero. The post-layout simulation results demonstrate that this LDO has robust system stability, a high open-loop gain, and a high unit-gain frequency,which lead to excellent regulation and transient response performance. The line and load regulation are 27μV/V and 3.78μV/mA, and the overshoots of the output voltage are less than 30mV,while the dropout voltage is 120mV for a 150mA load current.
提出了LDO,其基于缓慢滚降式频率补偿方法,通过在电路中引入三个极零对(极零对的产生没有增加静态功耗),不仅克服了常规LDO不能使用低等效串联电阻、低成本陶瓷输出电容的缺点,而且确保了系统在整个负载和输入电压变化范围内稳定工作.由于LDO通常给高性能模拟电路供电,因此其输出电压精度至关重要;而该补偿方法能满足高环路增益、高单位增益带宽的设计要求,从而大幅提高LDO的精度.该LDO基于0.5μm CMOS工艺实现.后仿结果表明,即使在低压满负载条件下,其开环DC增益仍高于70dB,满载时单位增益带宽可达3MHz,线性调整率和负载调整率分别为27μV/V和3.78μV/mA,过冲和欠冲电压均小于30mV,负载电流为150mA时的漏失电压(dropout电压)仅为120mV.
