摘要
本文提出了一种二维DCT快速算法的FPGA实现结构,采用行列快速算法将二维DCT分解成两个一维DCT实现,其中一维DCT借鉴Loeffler DCT算法,采用并行的流水线结构,提高电路的数据吞吐率和运算速度,通过系数矩阵的简化和蝶形运算结构的等价减少乘法器的消耗,一维DCT核消耗16个乘法器。转置RAM采用8片双口RAM,一个时钟可以完成8个数据读写。实验结果验证了二维DCT核设计的正确性,该电路结构消耗资源少,布线简单,功耗小,适合图像的实时处理。
In this paper a fast Discrete Cosine Transform （DCT） implementation architecture using FPGA is presented. The architecture uses a row-column decomposition to implement a 2-D DCT using twO 1-D DCT in series, The 1-D DCT processor is realized by optimizing the Loeffler DCT with parallel- pipeline architecture, which makes the circuit work with high data throughput and speed, and it reduces the number of multipliers by .simplifying the coefficient matrix and modifying the butterfly architecture, The 1-D DCT processor requires 16 multipliers, The transposition memory uses 8 Dual-Port rams, which can do eight reads and writes in one clock, Experimental results show that the design is correct. The circuit structure has the advantages of small chip size, simple wiring and low-power, which is extremely suitable to real-time image processing
出处
《电子质量》
2008年第2期5-7,22,共4页
Electronics Quality
