摘要
本文采用软硬件协同设计技术,提出以寄存器簇为粒度对嵌入式处理器寄存器堆进行功耗管理的方法.在软件方面,面向寄存器簇的编译优化使循环程序段中寄存器的编号尽可能相邻;在硬件方面,采用寄存器簇缓冲器过滤对寄存器堆的访问并降低其动态功耗,采用基于寄存器簇的动态电压调节电路和门控预充电路降低存储单元和位线的泄漏功耗.实验结果表明,本文方法将寄存器堆的总功耗降低约44.7%,比传统方法达到了功耗、面积和延迟的更优折衷.
In this paper, we propose the cluster-based power management mechanism, which uses register cluster as the power management granularity. Specifically, the cluster-oriented compiler makes the register numbers in loops as continuous as possible to offer more opportunities for run-time power management,and the cluster-based run-time power manager employs a register cluster buffer to filter accesses to the register file for dynamic power saving. The dynamic voltage scaling and gated orecharge circuits are also well utilized to reduce the leakage of bitceUs and bitlines. Averagely, the total register tile power is reduced by 44.7 %. with. traditional approaches, the hardware/software co-design approach proposed in this paper achieves better power,area and delay tradeoffs for register files in embedded processors.
出处
《电子学报》
EI
CAS
CSCD
北大核心
2008年第2期278-284,共7页
Acta Electronica Sinica
基金
国家863高技术研究发展计划(No.2006AA010202)
