摘要
卷积码作为通信系统中重要的编码方式,以其良好的编码性能,合理的译码方法,被广泛应用。本文在介绍卷积码原理的基础上,详细阐述了基于FPGA的卷积码的编/译码器的设计。值得一提的是,卷积码的译码采用维特比译码算法,利用了状态路径度量计算、保存路径转移过程和回溯译码等方法,在硬件实现上能有效地减少存储量、降低功耗,提高整个编/译码器的性能。最后进行了模拟仿真,结果显示编译码的效果比较理想,达到了设计的目的。
As the important coding method in the communication system, convolutional code has been extensively applied. Based on introduced the theory of the convolutional code, the design of the encoder and viterbi decoder are comprehensively discussed. This paper presents some efficient methods to reduce the number of bits to represent the path metrics and the number of saving paths in the process of tracking back. Consequently, the RAM size needed for saving metrics and paths as well as the power consumption are sharply decreased. The simulation result proves that the design process is right.
出处
《电子测量技术》
2008年第2期116-118,共3页
Electronic Measurement Technology
基金
海军工程大学自然科学基金资助项目(HGDJJ06012)
