摘要
文中设计了一种基于"移位-加"的专用常数乘加器来实现常系数滤波器的乘加运算。该常数乘加器基于CSD编码技术,采用3-2压缩器,并以华莱士树为其基本结构,以全并行算法来实现其乘加运算,且采取了先进的Three-Greedy连线算法来优化此乘加结构的速度。此乘加结构与传统的直接实现结构相比运算速度明显提高,与应用在通用乘法器的并行乘加器相比又具有较小的面积。所设计的乘加单元已应用在了一种高速D/A转换芯片中的内插滤波器中。
This paper implements a kind of high-speed constant multiplier-adder unit, which is based on shift-add operation. This multiplier-adder unit is based on CSD coding and adopts both 3-2 compressor and Wallace tree, its multiply-add operation is realized by entire parallel approach, and Three-Greedy connection algorithm is applied to this unit to improve its speed. As a result, this new multiplier-adder unit has a significant speed advantage compared with the traditional direct structure. Moreover, it occupied smaller area than parallel multiplier-adder unit which is applied in general multiplier. This unit has been applied in a interpolation filter of a high-speed DAC chip.
出处
《仪器仪表用户》
2008年第2期82-84,共3页
Instrumentation
