摘要
提出了一种片内存储器的可测性设计方法。在详细分析了边界扫描技术的结构,功能与控制原理的基础上,设计了一种存储器测试接口。该接口符合JTAG标准(IEEE1149.1标准),其中包含了标准的指令寄存器设计,用来控制访问不同的扫描链。在权衡了测试效率和芯片面积的基础上,提出了一种在线测试器电路的设计方法。实验表明,该测试电路可以以小的面积开销而节省大量测试时间。
This paper presents a testable design method for the embedded memories in an object System-on-a-chip （SoC）. By the analysis of the boundary-scan-technique （BST）, which include the structure, function and control, a Flash TAP （Test Access Port） is designed to test the embedded Flash. The interface feature complies with the JTAG specification （IEEE std. 1149. 1）, and it contains the standard instruction register, which can select different scan chains and other control registers. By the trade-off between the test time and the circuit area, an IST （In System Test ） circuit is designed in the SoC. Experiment results on the embedded memory have shown that the proposed method costs small tesing timing by the use of IST.
出处
《电子器件》
CAS
2008年第2期568-571,共4页
Chinese Journal of Electron Devices
