摘要
提出一种时钟树布线算法,在给定偏差约束下,采用新的匹配策略考虑偏差约束进行局部拓扑优化,优先匹配延迟目标大的结点,将其置于时钟树拓扑结构底层;结合缓冲器的插入,抑制了蛇行线的产生.实验结果表明,对使用过时钟偏差调度算法优化后的电路,该算法可在时钟布线阶段有效地减少时钟线网中连线与缓冲器的总电容.
This paper proposes a new algorithm for prescribed skew clock routing. It employs a novel merging strategy in conjunction with local topology optimizations for merging pairs and buffer insertions. Given prescribed skew constraints, nodes with larger delay target will first be considered and located at the bottom levels of the clock tree, an effective step to prevent detour wires. Experimental results show that the proposed algorithm can largely reduce total wire and buffer capacitance during clock routing, for the benchmark circuits that have been optimized by clock skew scheduling.
出处
《计算机辅助设计与图形学学报》
EI
CSCD
北大核心
2008年第4期452-458,共7页
Journal of Computer-Aided Design & Computer Graphics
基金
国家“八六三”高技术研究发展计划(2004AA1Z1010)
