摘要
针对通信过程中多时钟域之间的亚稳态现象,分析了几种同步器在集成电路异步设计中的应用。采用异步FIFO法设计ATM通信芯片中接口与内核的异步数据缓冲器。仿真验证结果表明该方法能使电路实现既定功能并提高其可靠性。
During the process of communication between different clock domains, metastability is likely to happen. This paper discusses several applications of different synchronizers in IC asynchronous design. Asynchronous FIFO is applied to the design of asynchronous data buffer between the interface and the core of ATM communication chip. The results of simulation show that the method can increase the reliability as well as realize the desired function.
出处
《计算机工程》
CAS
CSCD
北大核心
2008年第9期246-247,259,共3页
Computer Engineering
关键词
亚稳态
同步器
异步FIFO
格雷码
metastability
synchronizer
asynchronous FIFO
Gray code
