摘要
研究了烧结温度对TiO2压敏陶瓷显微结构、晶界势垒结构和电学性能的影响。采用扫描电镜(SEM)测试了不同烧结温度对TiO2陶瓷的显微结构;根据热电子发射理论,采用电学性能数据计算了不同烧结温度的晶界势垒结构;讨论了显微结构和势垒结构对TiO2压敏陶瓷电学性能的影响。实验结果表明:烧结温度必须高于致密化的初始温度,但烧结温度过高会形成大量氧空位而在晶粒中形成气孔,影响显微结构的均匀性和致密性,较适合的烧结温度为1 350℃。随烧结温度的增加,TiO2压敏陶瓷的晶粒尺寸长大,Nb5+的固溶度增加,势垒高度与势垒宽度增加,压敏电压降低,而非线性系数和介电常数增加。
Influences of sintering temperature（Ts） on microstructures, grain boundaries barrier structure （GBBS） and electrical properties of TiO2 varistors ceramics were investigated. Microstructures of TiO2 ceramics samples were measured through SEM. Based on the thermoelectronic emission theory, GBBS of TiO2 samples were calculated by analyzing electrical properties of the samples. Effects of microstructures and GBBS on both electrical properties of the samples were discussed. Ts need to be higher than the initiative temperature of TiO2 ceramics densification. While a too high Ts maybe induce a great deal of oxygen vacancies in TiO2 grains resulting in a non-homogeneous microstructure with more pores and incomplete densification. 1 350 ℃ is a suitable sintering temperature. With increasing of Ts ,grain size grows up and solid solubility of pentavalent Nb5^＋ cation solute in TiO2 grains increase. Barriers height, barriers width and non-linear coefficient increase while varistor voltages decrease with Ts in creasing.
出处
《压电与声光》
CSCD
北大核心
2008年第3期332-334,共3页
Piezoelectrics & Acoustooptics
基金
云南省科技攻关基金项目资助(2002GG09)
关键词
TIO2
压敏陶瓷
烧结温度
显微结构
势垒结构
TiO2
varistor ceramic
sintering temperature
mierostruetures
barriers structures
