摘要
文中设计了一款64点基-4FFT处理器,用改进的CORDIC(MVR-CORDIC)处理单元代替常规FFT处理器中的复数乘法器,改进的CORDIC处理单元在保证SQNR性能下,仅用极少次数的移位加法运算即可完成一次复数乘法,缩减了完成一次基本蝶形运算的时间并减小了面积开销。该FFT处理器结构采用两块独立的RAM,并对中间数据作"乒-乓"式存储操作以节省数据存储时间,从而提高完成一次FFT运算的速度。所设计的FFT处理器通过FPGA进行验证,结果表明平均完成一次64点FFT运算仅需要不到1μs。
A 64 point radix-4 FFT processor is designed. And the complex multiplier in trditional FFT precessor is substituted by the modified vector rotation CORDIC, the MVR-CORDIC complete a complex multiply by just a few of shift-add operartion at the guarantee of SQNR performance, so it diminishes the time of a butterfly operation and diminishes the whole area. Two independent RAM are employed in this FFT precessor to process and store the temporary data by a ＂Ping-Pang＂ mode and save the memory access time to improve the FFT opration time. This FFT processor is verified by the FPGA, The results show that no more than 1 μ s is consumed in one 64-point FFT operation.
出处
《电子与封装》
2008年第5期22-25,共4页
Electronics & Packaging
