摘要
研究了一种新的SHA-512算法基于FPGA的高速实现方案。为了获得较高的加密处理速度,本方案在关键计算路径上进行了加法器结构的优化;并且实现了分组数据输入与循环运算的并行进行,减少了加密一个分组所需的时钟周期数,提高了加密效率。在FPGA器件上实际运行,芯片工作在103 Mhz的时钟频率下,数据处理速率达到1300 Mbits/sec。
This article introduces a new high-speed implementation of SHA-512 algorithm. To improve the rate of encryption, the structure of adders on the critical path of calculation is optimized. By parallel inputting and calculating different blocks, the number of clock cycles needed for encrypting a single block is considerably reduced and the encrypting efficiency is improved. The chip works under a clock frequency of 103 Mhz when synthesized placed and routed in an FPGA device and achieves a throughput of 1300 Mbits/sec.
出处
《信息工程大学学报》
2008年第1期94-96,共3页
Journal of Information Engineering University
