摘要
受浮点操作的长流水线延迟及FPGA片上RAM端口数目的限制,传统FFT处理器的吞吐率通常只能达到每周期输出一个复数结果。本文用FPGA设计并实现了一种高吞吐率的IEEE754标准单精度浮点FFT处理器,通过改进蝶形计算单元的结构并重新组织FPGA片上RAM的访问,该处理器每周期平均可输出约两个复数计算结果,吞吐率约为传统FFT处理器吞吐率的两倍。对于1024点FFT变换,可在(512+10)*10=5220周期内完成。
In this paper, we design and implement a 32-bit IEEE 754 single precision floating-point FFT processor. Usually, limited by the long pipeline latency of floating-point operations and the number of the RAM ports on the FPGA chips the throughput of the traditional FFT processors can only reach approximately one result per cycle. Through making some improvements on the design of the butterfly unit architecture and reorganizing the RAM access, almost a throughput of 2 complex results per cycle can be obtained and twice performance over the traditional FFT processors can be achieved. As to a 1 024-point FFT transform, it can be finished in （512＋10） ＊ 10=5 220 cycles.
出处
《计算机工程与科学》
CSCD
2008年第7期98-99,117,共3页
Computer Engineering & Science
