摘要
嵌入式系统向小型化和低功耗的方向发展要求减小板级设计的面积提高速率.基于以上设计的要求对USB系统进行模块划分并利用Verilog语言设计出高速USB接口IP核.经过仿真验证,该IP核满足USB2.0的传输要求.
The embedded system is developing with small area and low power. It requires deduce the board design and in crease the speed. Debase above, this paper divide the USB modules and design the USB interface IP core with Verilog With simulation, this IP core contents the USB2. 0＇s request.
出处
《微电子学与计算机》
CSCD
北大核心
2008年第7期127-129,共3页
Microelectronics & Computer
