期刊文献+

嵌入式五级流水线CPU核的设计与实现 被引量:1

The Design- implementation of embedded five Stage Pipeline CPU Core
下载PDF
导出
摘要 本文基于FPGA平台设计并实现了一种嵌入式16位RISCCPU核。以MIPSCPU指令集为参考,完成指令集设计;对指令处理过程进行抽象,把指令分成取指、译码、执行、访存、写回五级流水处理,根据处理过程所需要的元件构建五级数据通路;针对流水线处理产生的数据相关构建旁路通路;根据五级数据通路及旁路通路所需要的协调信号构建控制通路;把数据通路和控制通路融合成CPU核。采用VHDL实现CPU核;在CPU核上运行测试程序,并给出仿真结果;在FPGA平台上对CPU核进行验证。结果表明了所设计CPU核的有效性。 An embedded 16-bit RISC CPU core was designed and implemented on FPGA. Refer to MIPS instruction set, the instruction set was finished; Analyzing the process of each instruction, the process was divided into five stages which is IF, ID, EXE, MEM, WB. Then the five stages data path was constructed according to work unit which is needed in the process; Aim at the data hazard which hap- pens in the pipeline, the forward path was constructed; the control path was constructed according to the data path; the CPU core was composed of data path and control path. The CPU core was implemented with VHDL; the test program was run at the CPU core, then the simulation was presented; the CPU core was verified at FPGA hardware terrace. The result shows that the CPU core is effective.
出处 《微计算机信息》 北大核心 2008年第29期32-34,共3页 Control & Automation
基金 广西壮族自治区科学技术厅资助项目"汽车运行状况智能监控与实时故障诊断系统"(桂科能063006-5G-3)
关键词 FPGA CPU核 数据通路 控制通路 FPGA CPU core Data path Control path
  • 相关文献

参考文献3

  • 1张杰.基于FPGA的八位RISC CPU的设计[J].微计算机信息,2006,22(12Z):155-157. 被引量:11
  • 2Zivkov, B: Ferguson, B. Gupta, M. R4200: a high-performance MIPS microprocessor for portables [C]. Compcon Spring '94, Digest of Papers. San Francisco, CA, USA: IEEE-CS Press, 28 Feb- 4 Mar 1994: 18-25.
  • 3Kyung-Sik Jang Kunieda, H. CPU core generation for hardware-software co-design .IEEE Asia Pacific Conference[C]. Seouh Circuits and Systems, 1996:306-309.

二级参考文献4

  • 1袁本荣,刘万春,贾云得,朱玉文.用Verilog HDL进行FPGA设计的一些基本方法[J].微计算机信息,2004,20(6):93-94. 被引量:23
  • 2袁俊泉,孙敏琪,曹瑞.Verilog数字系统设计教程[M].西安:西安电子科技大学出版社,2002.
  • 3J.Bhasjer著,孙海平等译.Verilog HDL综合实用教程[M].北京:清华大学出版社,2004.
  • 4http://www.xilinx-china.com/.

共引文献10

同被引文献13

  • 1王晓勇,张盛兵,黄嵩人.一种多发射DSP的数据相关控制[J].微型电脑应用,2011(11):56-58. 被引量:1
  • 2Hennessy J L, Patterson D A. Computer architecture - a quan- titative approach [ M ]. 4th ed. San Francisco : Morgan Kauf-mann Publishers ,2007.
  • 3张晨曦.计算机系统结构[M].第4版.北京:高等教育出版社,2006.
  • 4Sherwood T, Perelman E, Hamedy G, et al. Discovering and exploiting program phases [ J ]. IEEE Micro,2003,23 ( 6 ) : 84- 93.
  • 5Ho C Y, Chng K F, Yau C H, et al. A study of dynamic branch predictors : counter versus perceptron [ C ]//Proc of the inter- national conference on information technology. [ s. 1. ] : [ s. n. ] ,2007:528-563.
  • 6Jimenez D A, Lin C. Dynamic branch prediction with percep- tron[ C]//Proc of the 7th international symposium on high performance computer architecture. [ s. 1. ] : [ s. n. ], 2001 : 197-206.
  • 7Johnsonhaugh R, Schaefer M. Algorithms [ M ]. Beijing: Tsing- hua University Press,2007 : 195-197.
  • 8Pan Y, Mitra T. Characterizing embedded applications for in- struction-set extensible processors [ C ]//Proc of the 2004 in- ternational conference on compliers. [ s. 1. ] :ACM, 2004:67- 78.
  • 9潘琢金,郑彩平,杨华.流水线前端资源分配及其性能影响研究[J].计算机工程,2010,36(14):275-277. 被引量:2
  • 10薛杨.流水线技术性能评价与最佳段数选择[J].吉林省教育学院学报,2011,27(10):141-144. 被引量:1

引证文献1

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部