摘要
本文介绍了循环冗余检验（CRC）码的编／解码原理，给出了CRC编／解码的VHDL的算法实现，并在MODELSIM下给出仿真结果。
The theory of Cyclic Redundancy Check is presented in this paper, and then an example of CRC coder/decoder with VHDL is given, at last the results with Modelsim are checked.
出处
《导航》
2008年第3期73-75,共3页
