摘要
分析了基于FIPS的乘加器结构的VLSI实现随着操作数宽度的变化,速度和面积的变化趋势;提出了一种改进FIPS算法,解决了采用流水线结构的数据通路导致的数据迟滞问题。在SMIC0.18μm CMOS工艺下,基于该改进算法,设计了一个128位操作数位宽的模乘器,与基于原算法的设计相比,硬件面积增加约5%,效率提高了约42%。利用该模乘器进行1024位RSA运算时,速度可达1.1Mbps。
VLSI implementation of multiplier and accumulator based on FIPS was investigated. Differences in speed and area of implementations based on different operand width were analyzed. To solve the data latency problem caused by the pipeline data path, an improved FIPS algorithm was presented. And a modular multiplier with an operand width of 128 bits was designed based on the improved FIPS in 0. 18μm CMOS technology. Compared with designs based on the original FIPS, the optimized design achieved a 42% of speed improvement with only 5% of area increase. With the modular multiplier, a decryption rate of 1.1 Mbps could be achieved for 1 024-bit RSA.
出处
《微电子学》
CAS
CSCD
北大核心
2008年第5期609-613,共5页
Microelectronics
基金
国家自然科学基金资助项目(60576027
60544008)
国家863计划资助项目(2006AA01Z415)
