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同时多线程微处理器结构的性能功耗研究 被引量：2

Research on SMT power estimation model
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摘要 为同时多线程微处理器结构建立的准确的功耗评估模型,将可给出该结构中各部件的功耗使用情况,进而可通过调整部件电压或优化部件结构的方法,达到减少整体功耗的目的;同时,此功耗评估模型也可以作为高层功耗优化研究的测试平台,为系统级、软件级功耗优化研究提供支持。 Simultaneous Muhithreading （SMT） structure has become an important way to improve performance of microprocessors. The accurate power estimation model designed for SMT structure will be able to analyze the power consumption of each component in SMT,so that efforts can be made to reduce power consumption of some certain components;What is more,this power model can also be utilized as a testing platform for system level and software level power estimation research.
作者 郭松柳 汪东升 汤志忠
机构地区 微处理器与片上系统技术研究中心 清华大学计算机科学与技术系高性能计算研究所
出处 《计算机工程与应用》 CSCD 北大核心 2008年第28期4-8,共5页 Computer Engineering and Applications
基金 国家自然科学基金No.60573100~~
关键词 同时多线程微处理器(SMT) 功耗评估模型 CPU模拟器 Simultaneous Multithreading（SMT） power estimation model CPU simulator
分类号 TP3 [自动化与计算机技术—计算机科学与技术]
  • 相关文献

参考文献14

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二级参考文献74

  • 1[1]Nick Mitchell, Larry Carter, Jeanne Ferrante et al. ILP versus TLP on SMT. Supercomputing'99, 1999. http://www-cse.ucsd.edu/users/tullsen/research.html
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共引文献27

同被引文献17

  • 1王永文,张民选.高性能微处理器微体系结构级功耗模型及分析[J].计算机学报,2004,27(10):1320-1327. 被引量：5
  • 2徐勇军,韩银和,李华伟,李晓维.组合电路功耗敏感性统计分析[J].计算机辅助设计与图形学学报,2005,17(1):122-128. 被引量：4
  • 3黄琨,章隆兵,胡伟武,张戈.一种基于龙芯CPU的结构级功耗评估新方法[J].计算机研究与发展,2007,44(5):782-789. 被引量：4
  • 4Oswald Elisabeth. On side-channel attacks and the application of algorithmic countermeasures [D]. Graz, Austria: Graz University of Technology, 2003.
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  • 6Mangard Stefan. Calculation and simulation of the susceptibility of cryptographic devices to power-analysis attacks [D]. Graz, Austria.. Graz University of Technology, 2003.
  • 7Titlieh Stefan. Evaluation of side channel attack resistivity with rapid prototyping [D]. Graz, Austria: Graz University of Technology, 2003.
  • 8Li Huiyun, Theodore Markettos A, Moore Simon. Security evaluation against electromagnetic analysis at design time [C] //LNCS 3659: Proc of the 7th Int Workshop of Cryptographic Hardware and Embedded System. Berlin: Springer, 2005: 280-292.
  • 9Liu Zhenglin, Guo Xu, Chen Yicheng, et al. On the ability of AES S-boxes to secure against correlation power analysis [C] //LNCS 4464: Proc of the 3th Information Security Practice and Experience Conference. Berlin: Springer, 2007: 43-50.
  • 10Messerges Thomas S, Dabbish Ezzat A, Sloan Robert H. Examining smart-card security under the threat of power analysis attacks [J]. IEEE Trans on Computers, 2002, 51 (5) : 541-552.

引证文献2

二级引证文献4

计算机工程与应用
2008年 第28期

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