摘要
mpeg2的视频解码过程需要对片外存储器频繁的访问,在单总线结构的系统中,选取一定的总线仲裁策略以达到减少访问冲突,充分利用总线资源的目的。本文实现了解码系统中子模块与总线的接口电路,给出了不同仲裁策略下的RTL级仿真结果。
a large mount of data transfer between function modules and off-chip memory happened during mpeg2 video decoding process, so a proper bus arbitration is needed to make good use of bus resource. After building up the system, simulation result is provided.
出处
《信息通信》
2008年第5期15-16,共2页
Information & Communications
