期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

基于RAS结构优化测试时间和数据量的测试方案 被引量：2

A Test Scheme Based on RAS Structure to Reduced Test Volume and Time
下载PDF
导出
摘要 大规模高密度的集成电路在测试中遇到了测试数据量大,测试时间长等问题.对此,本文提出了一种带有折叠集的完全测试方案.该方案利用RAS(Random access scan)结构控制经输入精简的扫描单元,先生成若干折叠集检测电路中大部分的故障,然后直接控制扫描单元生成剩余故障的测试向量.本方案生成的折叠集故障检测率高,所需控制数据少.实验数据表明与同类方法相比,本方案能有效减少测试数据量和测试时间. The high density and large-scale IC meets lots of problems during test, such as huge amount of test data, long test time and so on. This paper presents a full test scheme by using folding test sets. Firstly several folding test sets are generated by random access scan structure in scan cells which are grouped by input reduction technology to detect most of the faults in circuit under test. Then data in scan ceils are modified directly to provide test patterns for the remaining faults. The folding test sets are efficient in detecting faults and they need less control information. Experiment results show that it has shorter test time and higher test data compression ratio comparing with other schemas based on RAS.
作者 梁华国 祝沈财 陈田 张念
机构地区 合肥工业大学计算机与信息学院
出处 《电子学报》 EI CAS CSCD 北大核心 2008年第12期2418-2422,共5页 Acta Electronica Sinica
基金 国家自然科学基金(No.90407008) 国家自然科学基金重点项目(No.60633060) 安徽省自然科学基金(No.050420103) 合肥工业大学研究发展基金(No.060501f) 安徽省青年教师基金(No.2006jql015)
关键词 输入精简 折叠计数器 数据压缩 随机访问扫描 input reduction folding counter data compression random access scan
分类号 TP306.2 [自动化与计算机技术—计算机系统结构]
  • 相关文献

参考文献8

  • 1彭喜元,俞洋.基于变游程编码的测试数据压缩算法[J].电子学报,2007,35(2):197-201. 被引量：33
  • 2Gerstendorfer S, Wunderlich H J. Minimized power consumption for scan-based BIST[A]. Proceeding of IEEE International Test Conference[C]. Atlantic, 1999.77 - 84.
  • 3Dong Hyun Baik, Kewal k. Saluja, Seiji Kajiharda Random access scan: a solution to test power, test data volume and test time [ A ]. International Conference On VLSI Design[C]. Mumbai ,2004. 883 -888.
  • 4Dong Hyun Baik, Kewal K. Saluja Progressive random access scan: a simultaneous solution to test power, test data volume and test time [ A ]. Proceedings of IEEE. Intemational test conference[C]. Austin, 2005. 359 - 368.
  • 5Hua-Guo Liang, Hans-Joachim Wunderlich. Sybille Hellebrand A mixed mode BIST scheme based on reseeding of fold counters[ A ]. Proceeding IEEE International Test Conference[C]. Atlantic City, 2000.778 - 784.
  • 6胡志国 梁华国.一种基于折叠序列重排并行低功耗自测试方案.上海师范大学学报：自然科学版,2005,34(5):103-107.
  • 7Fujiwara A. Yamamoto Parity-scan design to reduce the cost of test application[J]. Transaction on Computer-Aided Design of Circuits and Systems, 1993,12(10) : 1604 - 1611.
  • 8Chen C A, Gupta S K. A efficient BIST TPG design and test set compaction via input reduction [ J ]. Transaction on Computer- Aided Design of Circuits and Systems, 1998,17(8) :692 - 705.

二级参考文献11

  • 1韩银和,李晓维,徐勇军,李华伟.应用Variable-Tail编码压缩的测试资源划分方法[J].电子学报,2004,32(8):1346-1350. 被引量：27
  • 2A Jas, J Chosh-Dastidar. Scan vector compression/de-compression using statistical coding[ A]. IEEE VLSI Test Symposium [ C] .San Diego, California, USA. Apr, 1999.114 - 121.
  • 3T Yamaguchi, M Tilgner, et al. An efficient method for compressing test data [ A ]. the IEEE International Test Conference[ C ]. Washington DC, USA, 1997.79 - 88.
  • 4A Chandra, K Chakrabarty. System-on-a-chip test-data compression and decompression architectures based on golomb codes[ J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2001,20(3) :355 - 368.
  • 5A Chandra, K Chakrabarty. Frequency-directed run length (FDR) codes with application to system-on-a-chip test data compression[ A]. IEEE. VLSI Test Symposium[C].Marina Del Rey, Califomia, USA. 2001.42 - 47.
  • 6P T Gonciari,B M Al-Hashimi. Variable-length input Huffman coding for system-on-a-chip test [ J]. IEEE. Transactions on Computer-Aided Design of Integrated Circuits and Systems,2003,22(6) :783 - 796.
  • 7A Chandra, K Chakrabarty. A unified approach to reduce SOC test data volume, scan power and testing time [ J]. IEEE Tramactions on Conputer-Aided Design of Integrated Circuits and Systems,2003,22(3) :352- 362.
  • 8J Saxenu,K Butler, L Whetsel. An analysis of power reduction techniques in scan testing[ A ]. IEEE International Test Conference[C]. Baltimore, USA, 2001.670 - 677.
  • 9R Sankaralingam, R P Oruganfi, N A Touba. Static compaction techniques to control scan vector power dissipation [ A]. IEEE VLSI Test Symposium[ C] .Montreal, Canada,2000.35 - 40,
  • 10I Hamzaoglu, J H Patel. New techniques for deterministic test pattern generation [ A ]. IEEE. VLSI Test Symposium [ C ]. Princeton, New Jersey, USA, 1998.446 - 452.

共引文献33

同被引文献25

引证文献2

二级引证文献7

电子学报
2008年 第12期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部