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高码率LDPC码译码器的优化设计与实现 被引量：4

Optimized Decoder Design and Implement for High Rate LDPC Codes
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摘要 本文以CCSDS推荐的7/8码率LDPC码为例,提出了一种适于高码率LDPC码译码器的硬件结构优化方法。高码率的LDPC码通常也伴随着行重与列重的比例较高的问题。本方法是在拆分校验矩阵的基础上,优化常用的部分并行译码结构,降低了高码率LDPC码译码时存在的校验节点运算单元(CNU)与变量节点运算单元(VNU)之间的复杂度不平衡,并由此提高了译码器的时钟性能。实验证明,本文方案提供的结构与常用的部分并行译码结构相比,节省硬件资源为41%;采用与本文方案相同的硬件资源而未经矩阵拆分的部分并行译码方案的码速率为本文方案的75%。 This paper brings up with a hardware structure optimized method which is suitable for high code rate LDPC decoder, for example, CCSDS recommended LDPC （Low-Density Parity-Check code） code with code rate of 7/8. LDPC code with high code rate is usually concomitant with problem that row weight is far larger than the column weight. This optimized method is based on check matrix splitting, it also optimizes the common components of parallel decoder structure, and reduces complexity imbalance between Check Node processing Units （CNUs） and Variable Node processing Units （VNUs） existed in high code rate LDPC decoder. Thus, clock performance of the decoder is improved. Experiment has proved, compared with usual partial parallel decode structure, structure provided by this paper saves 41% hardware resources, and the code rate of partial parallel decode structure which adopts the same amount of hardware resources is just 75% than code rate of the structure in this paper.
作者 张靖琳 刘荣科 赵岭
机构地区 北京航空航天大学电子信息工程学院
出处 《电子与信息学报》 EI CSCD 北大核心 2009年第1期83-86,共4页 Journal of Electronics & Information Technology
基金 航天基金资助课题
关键词 LDPC码 译码器 优化设计 LDPC codes Decoder Optimized design
分类号 TN911.22 [电子电信—通信与信息系统]
  • 相关文献

参考文献8

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  • 3Consultative Committee for Space Data Systems. Low density parity check codes for use in near-earth and deep space applications. CCSDS 131.1-O-1, Orange Book, http://public, ccsds.org/publications/archive/13 lxlo ls.pdf, 2006. August.
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同被引文献35

  • 1GALLAGER R G.Low-Density Parity.Cheek Codes[M].Cambridge,MA:MIT Press,1963.
  • 2LI Z W,VIJAYA KUMAR B V K.A Class of Good Quasicyclic Low-density Parity Check Codes Based on Progressive Edge Growth Craph[C]//signals,Systems and Computers Conferenee Record of the Thirty-Eighth Asi-lomar Conference on,2004:1990-1994.
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  • 5Hong Ding, Shuai Yang, Wu Luo, et al. Design and Implementation for High Speed LDPC Decoder with Layered Decoding [A]. CMC'09 WRI International Conference on Communications and Mobile Computing [C]. Yunnan, 2009-01. 156:160.
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  • 7Ahmad Darabiha, Anthony Chan Carusone, Frank R. Kschischang. Multi-Gbit/sec Low Density Parity Check Decoders with Reduced Interconnect Complexity [A]. ISCAS 2005 IEEE International Symposium on Circuits and Systems [C]. 2005-05, 5:5194-5197.
  • 8Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, et al. An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications[J]. IEEE Journal of Solid-State Circuits. 2008, 43(3): 684-694.
  • 9Yeong-Luh, Chung-Jay Yang, Chun-Jung "Chen. A Shuffled Message-Passing Decoding Method for Memory-Based LDPC Decoders [A]. ISCAS 2009 IEEE International Symposium on Circuits and Systems [C]. Taipei, 2009-05. 892-895.
  • 10MacKay D J C and Neal R M. Near shannon limit performance of low density parity check codes [J]. Electronics Letters, 1996, 32(18): 1645-1646.

引证文献4

二级引证文献20

电子与信息学报
2009年 第1期

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