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电流舵D/A转换器的随机误差建模

Modeling of Random Error in Current-Steering D/A Converter
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摘要 电流源的失配是制约电流舵D/A转换器精度的一个重要因素。它是一个随机现象,需要用统计的观点进行分析。两个晶体管之间的失配,既与晶体管尺寸有关,又与晶体管之间的距离有关。以往的分析中,只考虑了尺寸相关项,而忽略了距离相关项。文章分析了基于距离相关项的随机误差,推导出每个数码的INL表达式,并用Matlab对不同开关序列下D/A转换器的成品率进行仿真,得出用SG算法优化开关序列,可大大减小距离相关项的影响。 The mismatch of two identical MOS transistors attributes to both the dimensions of MOSFETs and the distance between them. Previous works were done only based on the size-dependent term, with the distance term neglected. In this work, random error related to the distance term was analyzed, and the expression of INL for each code was calculated. The yields of DAC for different switching sequences were simulated with Matlab. It has been shown that the effect of distance term could be greatly reduced for SG arithmetic switching sequence.
作者 罗彦 王向展 于奇 沈路
机构地区 电子科技大学电子薄膜与集成器件国家重点实验室
出处 《微电子学》 CAS CSCD 北大核心 2009年第1期120-123,136,共5页 Microelectronics
关键词 电流舵D/A转换器 随机误差 距离相关项 积分误差 开关序列 Current-steering D/A converter Random error Distance term INL Switching sequence
分类号 TN792 [电子电信—电路与系统]
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参考文献9

  • 1江金光,何怡刚,吴杰.12位80MHz采样率具有梯度误差补偿的CMOS电流舵D/A转换器实现[J].Journal of Semiconductors,2003,24(12):1324-1329. 被引量：4
  • 2倪卫宁,耿学阳,石寅.A 12bit 300MHz Current-Steering CMOS D/A Converter[J].Journal of Semiconductors,2005,26(6):1129-1134. 被引量：1
  • 3PELGROM M, DUINMAIJER A, WELBERS A. Matching properties of MOS transistors [J]. IEEE J Sol Sta Circ, 1989, 24(5): 1433-1439.
  • 4BOSCH A V, STEYAERT M, SANSEN W. An accurate statistical yield model for CMOS current-steering D/A converters [C]// Proe IEEE Int Symp Circ Syst. 2000, (2): 105-108.
  • 5CONG Y H, GEIGER R L. Formulation of INL and DNL yield estimation in current-steering D/A converters[C]//Proc IEEE Int Symp Circ and Syst. 2002: 149-152.
  • 6KOSUNEN M, VANKKA J, TEIKARI I, et al. DNL and INL yield models for a current-steering D/A converter[C] // Proc IEEE Int Symp Circ Syst. Thailand. 2003:969-972.
  • 7RADULOV G I, HEGT J A. Brownian-bridge-based statistical analysis of the DAC INL caused by current mismatch[J]. IEEE Circ and Syst, 2007, 54(2): 146-150.
  • 8BARRANCO B L, GOTARREDONA T S. On an efficient CAD implementation of the distance term in Pelgroin's mismatch model [J]. IEEE Comp Aid Des Integr Cite And Syst, 2007, 26(8): 1534-1538.
  • 9CONG Y H, GEIGER R L. Switching sequence optimization for gradient error compensation in thermometer decoded DAC arrays [J]. IEEE Circ and Syst, 2000, 47(7): 585-595.

二级参考文献27

  • 1Lin Chihung,Bult K. A 10-b 500-M sample/s CMOS DAC in0. 6mm. IEEE J Solid-State Circuits,1998,33(12) :1948.
  • 2Marques A, Bastos J, Steyaert M, et al. A current steering architecture for 12-bit high-speed D/A converters. IEEE Circuits and Systems International Conference, 1998:23.
  • 3Van der Plas G A M,Jan V,Will S,et al. A 14-bit intrinsic accuracy Q^2 random walk CMOS DAC. IEEE J Solid-State Circuits, 1999,34(12) :1708.
  • 4Bastos J,Augusto M,Marques A,et al. A 12-bit intrinsic accuracy high-speed CMOS DAC. IEEE J Solid-State Circuits,1998,33(12) :1959.
  • 5Pelgrom M J M,Duinmaijeret A C J,Welberas A P G,et al.Matching properties of MOS transistors. IEEE J Solid-State Circuits, 1989,22(5):1433.
  • 6Takakura H, Yokoyama M, Yamaguchi A. A 10 bit 80 MHz glitchless CMOS D/A converter. Proc IEEE Custom Integrated Circuits Conference, 1991 :26. 5.1.
  • 7Analog Device Inc. , Data Sheet: AD 9 7 5 3 12-bit 3 0 0 MSPS high speed TxDAC+D/A converter,2003.
  • 8Schoeff J A. Aninherentlymonotonic 12bit DAC. IEEE J SolidState Circuits, 1979 ,SC-14(12): 904
  • 9Bugeja A R, Song B S. A self-trimming 14-b 100-MS/s CMOS DAC. IEEE J Solid-State Circuit s, 2000,35 (12): 1841
  • 10Bujeja A R,Song B S,Rakers P L,et al. A 14-b 100-MS/s CMOS DAC designed for spectral performance. IEEE J SolidState Circuits, 1999,34(12): 1719

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微电子学
2009年 第1期

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