摘要
在我们设计的北京谱仪第三代μ子鉴别器电子学读出系统中,一条数据链上连接了16块前端电路板(FEC),每块板上均放置一片FPGA芯片。通过研究和试验,在Altera公司提供的原PS配置方式的基础上增加LVDS驱动和控制芯片,实现了在30m外同时配置16块FPGA芯片;同时,也实现了利用单片机对FPGA配置芯片做JTAG方式编程,从而解决了所有的配置编程问题。
A read out system for muon counter of BESⅢ was developed at USTC. In the system, a data chain connects 16 front-end circuit board （FEC）, with an FPGA on each of the FECs. A method using PS mode to configure 16 FPGA chips from 30 m away by LVDS driving and a control chip, was introduced. Another method using MCU to configure the FPGA device in JTAG mode was also presented. SCM has also realized the use of the FPGA configuration chip JTAG programming methods to solve all kinds of the problem-targeted programming.
出处
《核技术》
CAS
CSCD
北大核心
2008年第10期786-790,共5页
Nuclear Techniques
基金
国家大科学工程北京正负电子对撞机升级项目(BEPCⅡ)资助
