摘要
在新一代视频压缩编码标准H.264中,亮度和色度的残差数据采用了自适应变长编码的方法.根据CAVLC熵编码的特点,提出了一种根据码表的前导零个数进行变长分组的优化VLD结构,并在此基础上设计了CAVLC硬件解码器.基于上述方法实现的CAVLC硬件结构通过了RTL级仿真和综合,并在Spartan3 XC3S2000的FPGA平台上进行了验证,在133 MHz工作频率下可以满足H.264标准Baseline档次30帧/s分辨率为352×288标准视频序列的实时解码.
In H.264,the residual data is encoded by CAVLC.According to the characteristic of CAVLC,an optimized VLD architecture of variable-length group based on number of leading zeros is proposed for H.264 CAVLC hardware decoder.The decoder has passed RTL class emulation and synthesis,and has been verified on Spartan3 XC3S2000 FPGA platform.Under 133 MHz working frequency,the CAVLC decoder can satisfy the quality and speed requirements of real-time video decoding on Baseline profile of H.264 with fps of 30F/s and resolution of 352×288.
出处
《东北师大学报（自然科学版）》
CAS
CSCD
北大核心
2009年第1期57-60,共4页
Journal of Northeast Normal University(Natural Science Edition)
基金
国家自然科学基金资助项目(60471009)
