摘要
介绍了AVR单片机与FPGA的总线接口的设计与实现,采用ATmega128微控制器与Altera公司的Cy-clone系列芯片EP1C6Q240I7进行硬件设计,详细阐述了硬件电路的结构,给出了基于硬件描述语言Verilog HDL的接口的设计及其仿真波形.总线接口的设计是为了解决串行数据传输速度慢的问题,方法采用FPGA来实现并行数据的传输.最后结果是设计的Verilog程序符合并行数据传输的要求,并验证了并行数据传输模式远远优越于传统的串行传输模式.
The design and implementation of AVR MCU and FPGA bus interface are introduced, using ATmega128 mierocontroller and Altera＇s Cyclone serial chip EP1C6Q24017 for hardware design. The structure of hardware circuit is elaborated in detail and the interface design and its simulation waveforms are presented using the hardware language of Verilog HDL. In order to solve the problem of the slow transmission speed of the serial data,we need design the bus interface. The method of the design is that we can use FPGA to realize the transmission of parallel data. At last, we find that the program of Verilog accords with the demand of the parallel data transmission. Moreover, it verifies that the transmission model of the parallel data is superior to the traditional transmission model of the serial data.
出处
《兰州交通大学学报》
CAS
2009年第1期79-81,共3页
Journal of Lanzhou Jiaotong University
基金
国家重点新产品计划LDJLZ-Ⅱ型全电子计算机联锁系统(2006GRG10002)
