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CoreConnect多级高速片上总线互连结构研究 被引量:1

CoreConnect Multi-layer High Performance on Chip Bus Structure
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摘要 本文介绍了SoC片上总线结构,对CoreConnect协议规范进行详细阐述,重点研究了其多级总线互连结构及功能和效率上的特性。该总线结构适用于具有高性能和高灵活性要求的SoC+ASIC设计环境。 With the development of SoC' s on - Chip bus, the CoreConnect protocol is described in detail and the multi - layer interconnect structure as well as the function and efficiency of this protocol is emphasized. It is an OCB designed for SoC plus ASIC environment with special requirement for performance and flexibility.
作者 沈智芳
出处 《湖北第二师范学院学报》 2009年第2期79-82,共4页 Journal of Hubei University of Education
关键词 片上总线 SOC CoreConnect on-Chip bus System - on - Chip CoreConnect
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参考文献4

  • 1.IBM128-bit Processor Local Bus Architecture Specifi-cations Version 4.6[]..2004
  • 2Bricaud P.J.EP reuse creation for system-on-a-chip design,Custom Integrated Circuits[].Proceedings of theIEEE.1999
  • 3IBM Inc.On-Chip Peripheral Bus Architecture Specifications[]..2001
  • 4IBM Inc.32-Bit Device Control Register Bus Architecture Specifications[]..2000

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