摘要
提出一种算法，用来产生组合逻辑电路中每个“总是0”和“总是1”单故障的完全测试集。该算法已编成程序用来处理大规模集成电路，它以布尔差分的某些特性为基础，能有效地产生完全测试集。对透彻了解不可检测故障、可检测单故障的测试以及电路冗余性三者之间的关系，作了讨论。
An algorithm for generating the complete test set of each stuck-at-0 (s-a-0) and stuck-at-1 (s-a-1) single fault in a combinational logic circuit is presented. The algorithm has been programmed to handle large scale integrated circuits and it is based on some properties of Boolean differences that make the generation of the complete test set very efficient.Some discussion is given to provide some insight into the relationship among undetectable faults, tests for detectable single faults, and circuit redundancies.
出处
《电机与控制学报》
EI
CSCD
1998年第2期129-132,共4页
Electric Machines and Control
关键词
逻辑电路
故障诊断
完全测试集
logic circuits
fault detect
fault diagnosis
complete test sets
