摘要
提出一种新型的基于FPGA硬件实现的SMS4分组密码算法电路设计。相对于常用的流水线设计方法和迭代设计方法,此设计将流水线和迭代运算相结合,结合了前者较高处理速度和后者较小实现面积的优点,达到了较好的性能,对WLAN商用密码算法的FPGA硬件实现有参考意义。通过Quartus II 8.0软件时序仿真验证了此设计的正确性,并使用以Cyclone II FPGA芯片为核心的DE2开发板验证了此设计的可实现性。
This paper points out a novel FPGA-based design method of SMS4 block cipher algorithm. Comparing with general design methods of SMS4 block cipher algorithm, such as pipeline method and iteration method, this novel design integrates pipeline with iteration calculation, while the quality of quick processing speed and small resource occupation coefficient are combined. It is a value exploration of FPGA-based hardware realization of business WLAN cipher algorithm. The function of this design is simulated by Quartus Ⅱ 8.0, and the whole design is realized on the DE2 development board.
出处
《电子技术应用》
北大核心
2009年第6期26-29,33,共5页
Application of Electronic Technique
