摘要
新一代卫星数字视频广播系统标准（DVB—S2）采用了功能强大的BCH＋LDPC信道编码方式，有效地降低了系统的解调门限，距离理论的香农极限只有0．7～1dB。本文首先对DVB-S2中BCH＋LDPC级联码性能进行分析，验证了级联码优越的性能，证明了BCH码在FEC系统中的作用。针对DVB—S2系统的特点，在传统译码的基础上采用并行译码提高译码速度。译码的3个部分计算校正子、计算关键方程、钱氏搜索均采用适合并行译码方式的设计。针对并行方式带来的硬件复杂度的上升，采用共享公共因子、时分复用等方式来降低一定的硬件复杂度。最后在FPGA上设计并实现了DVB—S2标准中BCH（14400，14232）的8位并行译码器。该译码器占用芯片逻辑单元数为8561，最高时钟频率为71．5MHZ，符合DVB—S2的要求。
DVB-2, the new generation transmission specification for satellite broad-band applications, adopts a scheme of channel coding which carries out concatenation of BCH outer coder and LDPC inner coder. The powerful FEC system effectively reduces the system demodulation threshold, allowing Quasi-Error-Free operation at about 0. 7-1 dB from the Shanon limit. In this paper, the performance of the BCH＋LDPC concatenated code in DVB- S2 is analyzed firstly and the excellent performance of concatenated code is validated. The role of BCH code in the FEC system is demonstrated. For the characteristics of DVB-S2 system, a parallel decoder based on traditional decoder is designed. This decoder can improve the rate of decode. The designing of Syndrome, BM, Chien Search adapt to parallel decoding. The hardware complexity is reduced by sharing public factors and time division multi- plexing. Finally,the 8-bits parallel decoder of BCH（14400,14232） in DVB-S2 is designed and implemented on FP-GA. The decoder use 8561 logic units of the chip and the fastest rate of the clock is 71.5 MHZ,the results meet the requirements of DVB-S2 system.
出处
《桂林电子科技大学学报》
2009年第3期222-225,共4页
Journal of Guilin University of Electronic Technology
