摘要
提出了一种改进的行式二维小波变换器结构,设计了位平面并行的位平面编码器和四级流水线结构的算术编码器,并将其整合于一个SoPC中,实现了JPEG2000编码系统。整个设计通过Altera公司Stratix Ⅱ系列的EP2S60F1020C5平台验证,在最高时钟频率98 MHz下能达到编码分辨率512×512、灰度图像52帧/s的速度,满足了实时编码的要求。
This paper proposes an improved architecture of two-dimensional wavelet transformer, designs a parallel bit-plane encoder and a four-pipeline arithmetic encoder, then integrates the three modules into a SoPC. The JPEG2000 coding system is tested on the EP2S60F1020C5, at the highest clock frequency of 98 MHz, it can process 52 gray images with the resolution of 512×512 in a second, which meets the requirement of real-time encoding.
出处
《电子技术应用》
北大核心
2009年第9期16-19,共4页
Application of Electronic Technique
