摘要
设计基于FPGA的8段数码管动态显示IP核，介绍8段数码管内部结构及其驱动显示方式和IP核设计方法．给出8段数码管动态显示IP核的VerilogHDL程序源代码及其C语言驱动程序。此IP核可例化成1～8个共阴极（或共阳极）数码管控制器，能方便地控制1～8个数码管同时显示数字和小数点位。测试结果表明．该IP核工作可靠、稳定。可直接应用于电子设计中。
This paper designs the dynamic displaying IP core of the 8-segment numeric LED based on FPGA,and intro- duces the internal structure of 8-segment numeric LED and its driver display and IP core design method,gives the Verilog HDL source code and C language driver program of the 8-segment numeric dynamic displaying IP core.The core can be instantiated as one to eight common cathode （or common anode）eight segments LED controllors,which can easily control these LEDs to display figures and radix point at the same time.Testing result shows that the IP core is reliable and stable, and can be applied in electron design.
出处
《电子设计工程》
2009年第10期82-84,共3页
Electronic Design Engineering
基金
广西壮族自治区教育厅科研项目(200808LX382)
南宁师范高等专科学校科研项目(ZRYJRCYB-02)
