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一种用于音频系统单环多比特ΔΣ D/A的设计

Single-Loop Multi-Bit High Resolution ΔΣ D/A for Audio System
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摘要 在1.8V电压下,使用UMC0.18μm混合信号工艺,设计实现了一个用于音频系统的19位20kHz数模转换器(DAC),其中包括了一个单环多比特Δ∑调制器和一个用于平滑效果的开关电容滤波器(SCF);仿真结果表明,在64倍过采样率、5bit信号量化时,DAC能够实现17.22bit的转换精度,模拟电路部分功耗只有6.9mW,考虑到数字部分,功耗和品质因素(FOM)值P/(2×BW×2ENOB)≤3pJ/step;芯片版图面积约为1.4mm×1.6mm。 A 19 bit 20 kHz digital to analog DAC was designed in UMC 0.18 μm CMOS technology with 1.8 V power supply. The DAC includes a single-loop multi-bit △∑ modulator and a switched capacitor filter. According to the simulation in spectre-verilog, it can realize 17.22 bit resolutions under 64 times over-sample ratio while in 5-bit quantization. The power used in analog part is only 6. 9 mW, considering the consumption of digital part, FOM value is smaller than 3 pJ/stcp, the whole chip size including PAD is 1.4 mm × 1.6 mm.
出处 《半导体技术》 CAS CSCD 北大核心 2009年第10期1027-1031,共5页 Semiconductor Technology
基金 "十一五"863计划重点项目(2008AA010708)
关键词 DAC Δ∑调制器 开关电容滤波器 FOM DAC converter ΔΣ modulator SCF FOM
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参考文献7

  • 1DEERTS Y, STEYAERT M, SANSEN W. Design of multi-bit delta-sigma A/D converters [ M ]. Germany : Springer, 2002 : 31- 43,149.
  • 2BREEMS L J, DIJKMANS E C, HUIJSING H. A quadrature data-dependent DEM algorithm to improve imagerejection of a complex ΣΔ modulator [ C ]//Proc of ISSCC. San Francisco, CA, USA, 2001:48-49.
  • 3BAIRD R T, FIEZ T S. Linearity enhancement of multibit ΔΣ A/D and D/A converters using data weighted averaging [J]. IEEE Trans on Circuits and Systems-II: Analog and Digital Signal Proc, 1995,42(12) :753-762.
  • 4FUJIMORI I, SUGIMOTO T. A 1.5 V, 4.1 mW dual-channel audio delta-sigma DA converter [J]. IEEE JSSC, 1998, 33 (12) :60-61.
  • 5van TUIJL A J M, van den HOMBERG J, REEFMAN D, et al. A 128 fs multi-bit ΣΔ CMOS audio DAC with real-time DEM and 115 dB SFDR [C] // Proc of ISSCC. San Francisco, California, USA, 2004 : 368-369.
  • 6JIANG Y, FRANCO M. A low-power multi-bit sigma delta modulator in 90-nm digital CMOS without DEM [J]. IEEE JSSC ,2005,40(12) :2428-2436.
  • 7NGUYEN K, BANDYOPADHYAY A, ADAMS B, et al. A 108 dB SNR 1.1 mW oversampling DAC with a three-level DEM technique [C]//Proc of Int SSC Conf. Lille, France, 2008 : 2592-2600.

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