摘要
为了解决视频信号的大量存储及视频延时问题,研究了一种以DDR2 SDRAM为存储体的高速海量FIFO设计方法。该方法通过采用FPGA对DDR2 SDRAM进行控制,以状态机来描述其各种时序操作,来完成DDR2 SDRAM的命令和数据的接口,从而实现数据的正确有序的存取。另外,流水式处理的方式,也保证了输入输出数据的连续性。经过最终硬件的成型和下载调试,验证了该方法的可行性和可靠性。该系统已经成功应用于视频的延时处理。
This paper presents a new design of a high speed and great capacity FIFO which can store a large number of high speed data, such as video signals. By the method of using FPGA to control the DDR2 SDRAM and the State Machine to describe the timing sequence operations, accomplishes the purpose of connecting the command and data interface from/to DDR2 SDRAM, so as to write and read the data accurately and orderly. What＇ s more, pipeline operation can insure the continuity of input and output data stream. The feasibility and the reliability of the method are proved by shaping the hardware and testing the data, and the method has been applied to video data processing.
出处
《信息技术》
2009年第9期95-97,共3页
Information Technology
