期刊文献+

提高过零检测精度的方法研究 被引量:14

Method Studies in Improving Accuracy of Zero-crossing Detection
下载PDF
导出
摘要 将运算放大器和专用快速比较器在过零检测中的应用进行了比较,对两种应用电路分别存在的问题,如相位误差、响应时间、对输入信号的要求等进行了分析,并提出了相应的解决办法。针对OCT电流测试系统,证明了信号的上升沿和稳定性对锁相精度的影响,提出采用运放构成两次过零比较,将入锁信号的上升沿时间△t从26.78μs降低到7.899μs,大大提升了入锁信号的的跟踪精度。 The applications of operational amplifier and professional comparator in zero-crossing detector are studied.Possible problems such as phase error, requirements of the input signals and response time,are analyzed,and the corresponding solutions are also put forward.The effect to phase-locking precision from signals rising edge and stability is verified for the OCT-current test system.Twice zero-crossing comparation is generated by adopting the applications of operational amplifier,which reduce the signal rising edge time from 26.78μs to 7.899μs,and greatly enhance the signal's tracking accuracy.
出处 《工业控制计算机》 2009年第10期80-81,88,共3页 Industrial Control Computer
基金 浙江省自然科学基金资助项目(M503207)资助
关键词 过零比较器 相位差 上升沿时间 稳定性 zero-crossing comparators,phase difference,rising edge time,stabilization
  • 相关文献

参考文献4

二级参考文献11

  • 1[2]Roland E. Best. Phase-locked Loops. Theory, Design, and Applications, America, 1984.
  • 2Razavi B, Wooley B A. Design techniques for high-speed, high-resolution comparators solid-state circuits[J]. IEEE Journal of Solid-State Circuits, 1992,27(12):1916-1926.
  • 3James H, Atherton H, Thomas S. An offset reduction technique for use with CMOS integrated comparators and amplifiers[J]. IEEE Journal of Solid-State Circuits, 1992,27(8):1168-1175.
  • 4Razavi B.Design of Analog CMOS Integraded Circuit[M]. International Editions, 2000.470-477.
  • 5AllenPE HolbergDR.CMOS Analog Circuit Design[M](英文版)[M].北京:电子工业出版社,2002.465-475.
  • 6Doernberg J, Gray P R, Hodges D A. A 10-bit 5-Msample/s CMOS two-step flash ADC[J]. IEEE Journal of Solid-State Circuits, 1989,24(2):241-249.
  • 7Sauer D J. Successive approximation analog to digital converter employing plural feedback digital to analog converters[P]. United States Patent, Patent Number: 5272481, Date: 1993.12.21.
  • 8Bult K, Geelen G J G M. A fast-settling CMOS op amp for SC circuits with 90-dB DC gain[J]. IEEE Journal of Solid-State Circuits, 1990,25(6):1379-1384.
  • 9Le H P, Zayegh A, Singh J. Performance analysis of optimised CMOS comparator[J]. Electronics Letters, 2003, 39(11):833-835.
  • 10Neubauer H, Desel T, Hauer H. A successive approximation A/D converter with 16 bit 200 kS/s in 0.6 μm CMOS using self calibration and low power techniques[A]. The 8th IEEE International Conference on Electronics, Circuits and Systems[C]. 2001. 2: 859-862.

共引文献19

同被引文献93

引证文献14

二级引证文献98

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部