摘要
基于IBM0.18μm标准CMOS工艺,设计了一种并行放大求和结构对数放大器(parallel-amplification parallel-summation logarithmic amplifier:PPLA)。该结构克服了连续检波式对数放大器(SDLA)延时长、易自激的缺点,在实现大动态范围的同时,无需反馈环路来稳定。该放大器应用于射频识别阅读器的ASK解调电路中,将大动态范围的输入信号压缩到接收机可以接收的范围。整个并行放大求和对数放大器获得70dB的动态范围、1MHz带宽、19mW功耗。
A parallel-amplification parallel-summation logarithmic amplifier （PPLA） was designed in IBM＇s 0. 18 μm CMOS technology. Compared with successive detection logarithmic amplifier （SDLA）, the PPLA has shorter delay time, and it is easier for the circuit to satisfy the stability requirements. It can be constructed to achieve high dynamic range without feedback loop. The PPLA was used in RFID reader as part of the ASK demodulation system to compress the high dynamic range input signal the RFID reader received. Simulation results showed that the PPLA bad a dynamic range of 70 dB, a bandwidth of 1 MHz, and a power dissipation of 19 mW.
出处
《微电子学》
CAS
CSCD
北大核心
2009年第5期627-630,共4页
Microelectronics
基金
上海AM基金(07SA04)
上海重点学科建设项目(B411)
关键词
射频识别阅读器
对数放大器
并行放大求和
ASK解调
RFID reader
Logarithmic amplifier
Parallel-amplification parallel-summation
ASK demodulation
