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可配置流处理器核心级指令设计及相关编译技术研究 被引量：4

Research on the Design of a Kernel-Level Instruction Set and the Compiler-Related Techniques for Configurable Stream Processors
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摘要 针对目前微处理器面对通用性、高性能、功耗效率的矛盾,我们提出了可配置流处理器的解决方案。本文重点研究了可配置流处理器中核心级指令设计及相关的编译技术,其核心设计思想是根据应用的计算特征设计流处理器中的核心级指令集,从而降低指令集硬件资源的需求。 To resolve the conflicts among generality, high performance and power efficiency of microprocessors, we propose a eonfigurable stream processor. This paper focuses on the design of a kernel-level instruction set and the compiler-related techniques for configurable stream processors, which reduces the hardware resource consumption by customizing the kernel-level instruction set for applications.
作者 何义 任巨 杨乾明 管茂林 文梅 张春元
机构地区 国防科技大学计算机学院
出处 《计算机工程与科学》 CSCD 北大核心 2009年第11期40-44,共5页 Computer Engineering & Science
基金 国家863计划资助项目(2007AA01Z286 2009AA01Z102) 国家自然科学基金资助项目(60673148 60703073) 国防科学技术大学计算机学院高性能计算联合博导组基金资助项目
关键词 可配置 指令集 流处理器 编译 configurable instruction set stream processor compilation
分类号 TP302 [自动化与计算机技术—计算机系统结构]
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参考文献17

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同被引文献43

  • 1王世好,王歆民,刘明业.嵌入式系统软硬件协同验证中软件验证方法[J].计算机研究与发展,2005,42(3):514-519. 被引量：10
  • 2Xu Guang,An Hong,et al.Performance analysis of the symmetric cryptograph on two stream architectures:Storm and GPU[C] //Proc of the 5th Int Conf on Intelligent Information Hiding and Multimedia Signal Processing.Piscataway,NJ:IEEE,2009:917-920.
  • 3Khailany B,Dally W,Rixner S,et al.Imagine:Media processing with streams[J].IEEE Micro,2001,21(2):35-46.
  • 4Yang Xuejun,Yan Xiaobo,et al.A 64-bit stream processor architecture for scientific applications[C] //Proc of the 34th Annual Int Symp on Computer Architecture.New York:ACM,2007:210-219.
  • 5Wen Mei,Nan Wu,Haiyan Li,et al.Multiple-dimension scalable adaptive stream architecture[C] //Proc of the Asia-Pacific Computer Systems Architecture Conference.Berlin:Springer,2004:199-211.
  • 6Agarwal V,Hrishikesh M S,Keckler S W,et al.Clock rate versus IPC:The end of the road for conventional microarchitectures[C] //Proc of the 27th Int Symp on Computer Architecture.New York:ACM,2000:248-259.
  • 7Swanson S,Michelson K,Shwerin A,et al.Dataflow:The road less complex[C] //Proc of the Workshop on Complexity-Effective Design (WCED),Held in Conjunction with the 30th Annual Int Symp on Computer Architecture.New York,ACM,2003.
  • 8Rixner S,Dally W J,Kapasi U J,et al.A bandwidth-efficient architecture for media processing[C] //Proc of the 31st Annual ACM//IEEE Int Symp on Microarchitecture.Los Alamitos:IEEE Computer Society,1998:3-13.
  • 9Cong Ming,et al.A feasibility study on hyperblock-based aggressive speculative execution model[C] //Proc of the Int Conf on Computer Engineering and Technology.Los Alamitos:IEEE Computer Society,2009:119-123.
  • 10Xu Guang,An Hong,et al.A wire delay scalable stream processor architecture[C] //Proc of the 13th IEEE Asia-Pacific Computer Systems Architecture Conference.Los Alamitos,AC:IEEE Computer Society,2008:1-8.

引证文献4

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计算机工程与科学
2009年 第11期

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