摘要
片上网络(Network On Chip,NoC)是最具潜力的下一代片上互连技术。但NoC架构的引入也带来了芯片设计复杂度的大幅提高,从而使得传统仿真方式会消耗过多的时间。提出了一种有效的基于FPGA器件的多核系统原型设计与性能评估方法。实现了一款集成了8个处理核的NoC架构下的多处理核系统原型,并通过两种实际应用对系统性能进行评估和探索。实验结果表明,该原型在矩阵乘法应用和JPEG图片解码应用中加速比最高分别可达到7.53和2.75。而相对于层次化总线架构,NoC架构的通信性能可提高5%～40%。
The Network-on-Chip （NoC） is a promising solution for the future on-chip interconnection. However, the NoC architecture brings the significant increase of design complexity, which may cause the unacceptable simulation time under the traditional simulation methods. This paper proposed an effective FPGA-based way for designing and evaluating the prototype of NoC system. A NoC-based multiprocessor system, which integrated 8 processor cores, is implemented in this paper. The system performance under two different real applications is evaluated and explored. The result shows that the speedup performance of this prototype can reach 7.53 in matrix multiplication and 2.75 in JPEG picture decoding, respectively. And, comparing to the hierarchy bus architecture, the NoC architecture can improve the communication performance by 5%-40%.
出处
《电子测量与仪器学报》
CSCD
2009年第11期89-94,共6页
Journal of Electronic Measurement and Instrumentation
基金
863计划(编号:2008AA01Z135)资助项目
教育部博士点基金(编号:20070359032)资助项目
关键词
片上网络
多核硬件原型
性能评估
network-on-chip
hardware prototype of multiprocessor
performance evaluation
