摘要
在诸如目标监视、雷达数据处理等需要对图像数据进行高速处理的数字系统中,大量利用同步动态存储器(SDRAM)作为数据的缓存。针对SDRAM的工作原理和时序特点,提出了一种基于FPGA的SDRAM控制器实现方法。采用硬件描述语言(VHDL)在Quartus7.2环境下进行了设计与仿真,较好地实现了各种工作状态之间的跳转,仿真结果也完全符合SDRAM所要求的控制时序。最后在Altera公司的FP-GA上利用设计的控制器对Micron公司的SDRAM进行了验证,监测结果显示,SDRAM能够很好地完成规定读写操作。参数化设计也使得该控制器具有较好的通用性。
In modern digital system such as target surveillance and image processing system, image data need to process and store by use of high speed and large capacity. Synchronous dynamic random access memory （SDRAM） was widely used as data buffer. Aimed at the working principle and the characteristics of time sequence, SDRAM controller implementation method was put forward based on FPGA. Using hardware description language （VHDL）, the design and simulation were performed under the environment of quartusT. 2, and the switching between various working states were realized. The simulation resuits coincide with control time sequence required by SDRAM. This design was tested on Altera＇s FPGA to control Micron＇s SDRAM, and the test results stipulated read and write. Parametric design allows showed that SDRAM can work regularly to perform the controller to have a good versatility.
出处
《火炮发射与控制学报》
北大核心
2009年第4期38-41,共4页
Journal of Gun Launch & Control
