摘要
VHDL电路的优化目标是充分利用CPLD/FPGA芯片的内部资源,使设计文件能适配到一定规模的CPLD/FPGA芯片中,并提高系统的工作速度和降低系统成本。分析VHDL语言的特点,并从设计思想、语句运用和描述方法等方面对电路进行优化,提出了利用串行化设计思想和外扩E2PROM的方法对VHDL电路进行优化,通过对比实验,验证了这两种方法能有效减少程序占用的宏单元(Macro Cell)。
The optimized design of VHDL is for making full use of hardware resources provided by CPLD/FPGA,making the design suit for certain scale of CPLD/FPGA chip,increasing the system＇s speed and reducing system＇s costs. The advantages of VHDL language are analysed and the circuit design is optimized from the design idea, the use of statements, coding style. In this paper, serial design methods and the use of E2PROM to optimize the circuit design are proposed, these two methods are proved to be effective in reducing Macro Cell occupied by the program.
出处
《现代电子技术》
2010年第3期191-193,共3页
Modern Electronics Technique
