期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

嵌套式稀疏网格随机配置法及其在随机门延时建模中的应用 被引量：2

Nested Sparse-grid Stochastic Collocation Method and Its Application to Gate Delay Modeling under Process Variations
下载PDF
导出
摘要 为了提高随机工艺偏差下门延时建模的计算精度和效率,提出一种基于扩展Gauss积分理论及嵌套式稀疏网格技术的随机配置门延时建模方法.首先采用参数空间中具有指数收敛特性的随机正交多项式对随机门延时进行逼近;然后针对现有的基于传统Gauss积分理论的稀疏网格随机配置法所用的配置点不具有嵌套特性的问题,利用单变量扩展Gauss积分理论及稀疏网格技术构造了一组嵌套式多变量Gauss积分点,将其作为随机门延时建模的配置点.这组配置点既具有Gauss积分点的高精度,又满足嵌套性质,且在低阶积分配置点上已经得到的门延时可以在高阶积分时重复使用.与现有的基于非嵌套式配置点的随机配置法相比,该方法的计算精度和效率可以得到很大的提升,数值实验结果也验证了该方法在计算精度和效率上的优势. In this paper,an extended Gaussian quadrature based nested sparse-grid stochastic collocation method（NSSCM） is proposed for further improving the computation accuracy and efficiency of stochastic gate delay modeling considering process variation.Firstly,the orthogonal polynomial bases in the stochastic space of gate parameters are employed in NSSCM to approximate the stochastic gate delay and exponential convergence rate is achieved.Secondly,the proposed NSSCM employs one-dimensional extended Gaussian quadrature points and sparse grid technique to construct the nested multidimensional collocation points.Compared with the existing non-nested sparse-grid stochastic collocation method（SSCM）,the nested collocation points used in NSSCM not only maintain the high computation precision of Gaussian quadrature,but also have the nested property to guarantee that gate delays obtained at low order collocation points can be reused in high order quadrature.The reuse of collocation points can remarkably improve the computation accuracy and efficiency of gate delay modeling.Experimental results demonstrated the merits of the proposed method.
作者 罗旭 杨帆 朱恒亮 陶俊 蔡伟 周电 曾璇
机构地区 复旦大学专用集成电路与系统国家重点实验室 Department of Mathematics Department of Electrical Engineering
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2010年第1期165-172,共8页 Journal of Computer-Aided Design & Computer Graphics
基金 国家自然科学基金(60976034,60676018,60806013,60673029) 国家十一五重大科技专项项目(2008ZX01035-001-06,2009ZX02023-4-3) 国家重点基础研究发展计划项目(2005CB321701) 教育部高等学校博士学科点专项科研基金(200802460068) 上海市领军人才项目上海市科学技术委员会国际科技合作基金项目(08510700100)
关键词 门延时 工艺偏差 扩展Gauss积分 嵌套式稀疏网格 随机配置法 gate delay process variations extended Gaussian quadrature nested sparse grid stochastic collocation method
分类号 TN47 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献18

  • 1Sapatnekar S. Timing [M]. Boston: Kluwer Academic Publishers, 2004.
  • 2Bhardwaj S, Ghanta P, Vrudhula S. A framework for statistical timing analysis using non linear delay and slew models [C] //Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, San Jose, 2006: 225-230.
  • 3Ghanem R G, Spanos P D. Stochastic t'inite elements: a spectral approach [M]. NewYork: Springer Verlag, 1991.
  • 4Vrudhula S, Wang J M, Ghanta P. Hermite polynomial based interconnect analysis in the presence of process variations [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25(10) : 2001-2011.
  • 5Zou Y, Cai Y C, Zhon Q, et al. Practical implementation of stochastic parameterized model order reduction via Hermite polynomial chaos [C] //Proceedings of IEEE Asia and South Pacific Design Automation Conference, Yokohama, 2007: 367-372.
  • 6Dongbin Xiu.Efficient Collocational Approach for Parametric Uncertainty Analysis[J].Communications in Computational Physics,2007,2(2):293-309. 被引量：9
  • 7Kumar S Y, Li J, Talarico C, et al. A probabilistic collocation method based statistical gate delay model considering process variations and multiple input switching [C]//Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Miinich, 2005:770-775.
  • 8Tao J, Zeng X, Cai W, et al. Stochastic sparse-grid collocation algorithm (SSCA) for periodic steady-state analysis of nonlinear system with process variations [C] // Proceedings of IEEE Asia and South Pacific Design Automation Conference, Yokohama, 2007: 474-479.
  • 9Zhu H L, Zeng X, Cai W, etal. A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology [C] //Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Nice, 2007:1-6.
  • 10Zhang W Y, Yu W J, Wang Z Y, et al. An efficient method for chip level statistical capacitance extraction considering process variations with spatial correlation [C] //Proceedings of the Design, Automation and Test in Europe, Miunich, 2008: 580-585.

二级参考文献19

  • 1张富彬,HO Ching-yen,彭思龙.静态时序分析及其在IC设计中的应用[J].电子器件,2006,29(4):1329-1333. 被引量：5
  • 2Visweswariah C, Ravindran K, Kalafala K, et al. First order incremental block based statistical timing analysis [C]// Proceedings of IEEE/ACM International Conference on Design Automation Conference, San Diego, 2004:331-336.
  • 3Chang H L, Zolotov V, Narayan S, et al. Parameterized block-based statistical timing analysis with non Gaussian parameters, nonlinear delay functions [C]//Proceedings of IEEE/ACM International Conference on Design Automation Conference, Anaheim, 2005: 71-76.
  • 4Zhan Y P, Strojwas A J, Li X, et al. Correlation-aware statistical timing analysis with non-Gaussian delay distributions [C] //Proceedings of IEEE/ACM International Conference on Design Automation Conference, Anaheim, 2005:77-82.
  • 5Zhang L Z, Chen W J, Hu Y H, et al. Correlation- preserved non-Gaussian statistical timing analysis with quadratie timing model [C] //Proceedings of IEEE/ACM International Conference on Design Automation Conference, Anaheim, 2005:83-88.
  • 6Khandelwal V, Srivastava A. A general framework for accurate statistical timing analysis considering correlations [C] //Proceedings of IEEE/ACM International Conference on Design Automation Conference, Anaheim, 2005:89-94.
  • 7Singh J, Sapatnekar S. Statistical timing analysis with correlated non Gaussian parameters using independent component analysis [C] //Proceedings of IEEE/ACM International Conference on Design Automation Conference, San Francisco, 2006:155-160.
  • 8Fang J, Luk W S, Zhao W Q. True worst-case clock skew estimation under process variations using affine arithmetic[J]. Chinese Journal of Electronics, 2007, 16(4) : 631-636.
  • 9Bhardwaj S, Ghanta P, Vrudhula S. A framework for statistical timing analysis using non-linear delay and slew models [C]//Proceedings of the IEEE/ACM International Conference on Computer Aided Design, San Jose, 2006:225-230.
  • 10Satish K Y, Li J, Talarico C, et al. A probabilistic collocation method based statistical gate delay model considering process variations and multiple input switching [C]//Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Messe Munich, 2005:770-775.

共引文献10

同被引文献8

引证文献2

二级引证文献2

计算机辅助设计与图形学学报
2010年 第1期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部